1. Field of the Invention
The present invention relates to the isolation of electrical elements of semiconductor devices. More particularly, the invention relates to a method of the isolation of electrical elements of semiconductor devices by means of trenches, and a semiconductor device having isolation regions according to the method of the present invention.
2. Description of the Prior Art
A trench technique for isolating several electrical elements included on a single chip in semiconductive integrated circuit devices has been used in recent semiconductor manufacture. This technique adapts a method for isolating electrical elements from each other by forming trenches on a semiconductor substrate through dry-etching and refilling the trenches with insulating materials. This reduces parasitic capacitance caused by packing the elements closer to each other to increase the density of the elements on the substrate.
FIG. 1 illustrates a semiconductor device having active regions 1 on which electrical elements are formed and which are isolated from neighboring active regions 1 by trenches 2, i.e. an isolation region.
The process for making the trenches 2 to isolate the electrical elements from each other is depicted in FIGS. 2A to 2E, which are sectional views taken along lines A--A' of FIG. 1.
As shown in FIG. 1, the trenches 2 may be narrow trenches 3 or relatively wide too.
The process for making the conventional trenches of FIG. 2 will now be described.
This process begins with the formation of a silicon pad oxide film 6 of a predetermined thickness on a silicon substrate 5 by a thermal oxidation treatment or a chemical vapor deposition. A silicon nitride layer (SiN) 7 is deposited on the pad oxide film 6 by a low pressure chemical vapor deposition (CVD), and a high temperature oxide film (HTO) 8 is formed thereon. These films serves as a masking layer when the silicon substrate 5 is selectively etched.
Subsequently, in order to distribute the surface of the substrate into each area, a photoresist film 9 is spin-coated on the high temperature oxide film 8, and exposed to light by photomask and developed to carry out a patterning process. The widths of apertures on which the photoresist film is removed, as shown in FIG. 2A, are different from each other, and these regions 3 and 4 define trench regions that are to be formed.
The high temperature oxide film 8 is selectively etched through dry-etching, (FIG. 2B) according to the patterns defined by the photoresist films 9. Parts of the nitride layer 7 and oxide film 6 underneath the apertures are then successively etched to be removed, using the high temperature oxide film 8 as an etching mask, and trenches are formed to a predetermined depth with an anisotropic etch step, as can be seen from FIG. 2C. A thin oxide film 10 is then formed on the inside of the trenches by a thermal oxidation process, (FIG. 2C) and the trenches are refilled with, e.g. a high temperature oxide film 11 (FIG. 2D). Due to the width difference between the narrow trench 3 and the broad trench 4, the narrower trench 3 is refilled enough to be higher than the high temperature oxide film 8'. On the other hand, the inside of the wider trench 4 is not refilled sufficiently, and the refilled layer inside the narrower trench 3 has a dimple D in the center thereof, ad shown in FIG. 2D.
Under the circumstances, the high temperature oxide film 11 refilled in the trenches and the high temperature oxide film 6 8' on the silicon nitride layer 7 are etched away through anisotropic etching, and the nitride layer 7 and the pad oxide film are etched away by a wet-etching method to expose the active regions of the substrate 5. The isolation region is then formed by the trenches, as shown in FIG. 2E, and electrical elements are formed on the active regions between the trenches.
As shown in the sectional structure of FIG. 2E, however, a step-like difference of the trench-refill material obviously appears according to the trench width, and this may cause a deterioration in step coverage of films deposited on the trench-refill material. For example, when a metal oxide semiconductive element is formed on the active regions and its gate electrode is expansively formed across the trench, delayed signals may be caused due to this step-like difference.
If the trenches of widely varying widths are filled, the narrow trench must be well overfilled in order for the wider one to be filled completely. Thus, the thickness of the top-surface-deposited film may vary, making planarization very difficult.
This is one reason why deep trenches refilled with CVD polysilicon of SiO2 cannot replace a process known as localized oxidation of silicon for isolation of elements (LOCOS) as an isolation technique for field regions of varying widths.